W971GG6：
Part No | Voltage | Speed | Temperature | Organization |
W971GG6JB | 1.8V±0.1V | 1066/800/667Mbps | C-temp, I-temp, Automotive | 64Mbit x16 8 Banks |
W971GG6KB | 1.8V±0.1V | 1066/800/667Mbps | C-temp, I-temp | 64Mbit x16 8 Banks |
W971GG6SB | 1.8V±0.1V | 1066/800/667Mbps | C-temp, I-temp, Automotive | 64Mbit x16 8 Banks |
◆Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
◆Double Data Rate architecture: two data transfers per clock cycle
◆CAS Latency: 3, 4, 5, 6 and 7
◆Burst Length: 4 and 8
◆Differential clock inputs (CLK and /CLK)
◆Data masks (DM) for write data
◆Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
◆Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
◆Auto-precharge operation for read and write bursts
◆Auto Refresh and Self Refresh modes
◆Precharged Power Down and Active Power Down
◆Write Data Mask
◆Write Latency = Read Latency - 1 (WL = RL - 1)
◆Interface: SSTL_18
W9725G：
Part No | Voltage | Speed | Temperature | Organization |
W9725G2JB | 1.8V±0.1V | 800/667Mbps | C-temp | 8Mbit x32 4 Banks |
W9725G6KB | 1.8V±0.1V | 1066/800/667Mbps | C-temp, I-temp, Automotive | 16Mbit x16 4 Banks |
◆Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
◆Double Data Rate architecture: two data transfers per clock cycle
◆CAS Latency: 3, 4, 5, 6 and 7
◆Burst Length: 4 and 8
◆Differential clock inputs (CLK and /CLK)
◆Data masks (DM) for write data
◆Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
◆Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
◆Auto-precharge operation for read and write bursts
◆Auto Refresh and Self Refresh modes
◆Precharged Power Down and Active Power Down
◆Write Data Mask
◆Write Latency = Read Latency - 1 (WL = RL - 1)
◆Interface: SSTL_18
W972GG6KB：
Part No | Voltage | Speed | Temperature | Organization |
W972GG6JB | 1.8V±0.1V | 1066/800/667Mbps | C-temp, I-temp, Automotive | 128Mbit x16 8 Banks |
W972GG6KB | 1.8V±0.1V | 1066/800/667Mbps | C-temp, I-temp, Automotive | 128Mbit x16 8 Banks |
◆Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
◆Double Data Rate architecture: two data transfers per clock cycle
◆CAS Latency: 3, 4, 5, 6 and 7
◆Burst Length: 4 and 8
◆Differential clock inputs (CLK and /CLK)
◆Data masks (DM) for write data
◆Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
◆Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
◆Auto-precharge operation for read and write bursts
◆Auto Refresh and Self Refresh modes
◆Precharged Power Down and Active Power Down
◆Write Data Mask
◆Write Latency = Read Latency - 1 (WL = RL - 1)
◆Interface: SSTL_18
W9751G6KB:
Part No | Voltage | Speed | Temperature | Organization |
W9751G6KB | 1.8V±0.1V | 1066/800/667Mbps | C-temp, I-temp, Automotive | 32Mbit x16 4 Banks |
◆Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
◆Double Data Rate architecture: two data transfers per clock cycle
◆CAS Latency: 3, 4, 5, 6 and 7
◆Burst Length: 4 and 8
◆Differential clock inputs (CLK and /CLK)
◆Data masks (DM) for write data
◆Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
◆Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
◆Auto-precharge operation for read and write bursts
◆Auto Refresh and Self Refresh modes
◆Precharged Power Down and Active Power Down
◆Write Data Mask
◆Write Latency = Read Latency - 1 (WL = RL - 1)
◆Interface: SSTL_18